
`include "common_header.verilog"

//  *************************************************************************
//  File : mdio_clk_genc
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited. 
//  Copyright (c) 2009 Morethanip, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Francois Balay
//  info@morethanip.com
//  *************************************************************************
//  Decription : MDC Management Clock Generation with programmable divisor
//  Version    : $Id: mdio_clk_genc.v,v 1.1.1.1 2009/04/03 07:20:04 dk Exp $
//  *************************************************************************

module mdio_clk_genc (

   reset,
   clk,
   divisor,
   clk_ena,
   mdio_clk);

input   reset;          //  Master Reset
input   clk;            //  Clock
input   [8:0] divisor;  //  divisor setting
output  clk_ena;        //  Clock Enable 
output  mdio_clk;       //  MDIO Clock

reg     clk_ena; 
reg     mdio_clk; 
reg     [9:0] cnt; 
reg     [9:0] divisor_div2; //  divisor divided by 2

wire    [9:0] divisor10;  //  divisor setting

assign divisor10 = {divisor, 1'b 0};    // multiply by 2

//  Clock Divider
//  -------------

always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      cnt          <= 10'h 0;	
      divisor_div2 <= 10'h 0;
      end
   else
      begin
      if (cnt == 10'h 0)        // >= divisor)
         begin
         cnt <= divisor10;        // 10'h 00;	
         end
      else
         begin
         cnt <= cnt - 10'h 01;	
         end

        if( cnt==10'h 00 )
        begin
                divisor_div2 <= {1'b 0, divisor10[9:1]}; //  divide by 2
        end

      end
   end

//  MDIO Clock Generation
//  ---------------------

always @(posedge reset or posedge clk)
   begin : process_2
   if (reset == 1'b 1)
      begin
      mdio_clk <= 1'b 0;   
      end
   else
      begin
      if (cnt < divisor_div2)
         begin
         mdio_clk <= 1'b 0;   
         end
      else
         begin
         mdio_clk <= 1'b 1;   
         end
      end
   end

//  Enable for MDIO Control
//  -----------------------

always @(posedge reset or posedge clk)
   begin : process_3
   if (reset == 1'b 1)
      begin
      clk_ena <= 1'b 0;   
      end
   else
      begin
      if (cnt == 10'h 00)        // divisor)
         begin
         clk_ena <= 1'b 1;   
         end
      else
         begin
         clk_ena <= 1'b 0;   
         end
      end
   end

endmodule // module mdio_clk_gen